ANTI-SEE PROTECTION TECHNIQUES FOR HIGH-SPEED ICs WITH A CURRENT-SWITCHING ARCHITECTURE

ABSTRACT

Protection against anti single event effects associated with strikes of energetic particles is provided in current-mode logic (CML) or similar integrated circuits (ICs) using a current-switching architecture.

TECHNICAL FIELD

The present application relates to high-speed data processing equipment that is capable of operating properly when subjected to radiation from natural and/or artificial sources. Such data processing equipment, for example, may include space-oriented electronics, deep sub-micron electronics, special equipment, etc.

BACKGROUND

Anti-SEE (single event effect) protection is vital for integrated circuits (ICs) such as those operating in outer space, and is becoming critical for ground-based circuits due to increasing miniaturization of their components. In integrated circuits (ICs) such as current-mode logic (CML) and similar ICs with a current-switching architecture, single-event effects (SEE) are associated with strikes of energetic particles. These strikes cause an electric charge to be generated in the IC's regions resulting in the appearance of short current pulses flowing into the heterojunction bipolar transistor's (HBT) collector node and out of its base, emitter, and substrate nodes.

FIG. 1 shows a model of a SEE in a heterojunction bipolar transistor (HBT) derived from G. Niu, R. Krithivasan, J. Cressler et al., “A Comparison of SEU Tolerance in High-Speed SiGe HBT Digital Logic Designed with Multiple Circuit Architectures,” IEEE Trans. On Nuclear Science, v. 49, No. 6, December 2002, pp. 3107-3114. The equivalent circuit shown in FIG. 1 describes three independent current sources i_(Bp), i_(Sp), and i_(En), which represent SEE-induced transient current pulses through the base, substrate, and emitter nodes correspondingly. The SEE-induced collector current i_(Cn) is then given by i_(Cn)=−(i_(Bp)+i_(Sp)+i_(Rn)).

A computer simulation of these current pulses in a silicon germanium (SiGe) HBT with a 0.2×0.72 μm² emitter area for a linear energy transfer (LET)=20 pC/μm is shown in FIG. 2. As can be seen, the collector and emitter currents run into the nodes, while the base and emitter currents are reversed. It is important to note that the collector current pulse is significantly higher than the base current pulse. Assuming a certain resistive termination at the collector, emitter, and base nodes, the described behavior results in a lower collector node voltage and a higher base node voltage. The changes in the emitter node voltage depend on the actual termination scheme.

There exist several techniques for anti-SEE protection including (i) triple majority voting described by R. Katz, R. Barto, P. McKerracher, B. Carkhuff, and R. Koga, in “SEU Hardening of Field Programmable Gate Arrays for Space Applications and Device Characterization” (unabridged version), IEEE Transactions on Nuclear Science, NS-41, pp. 2179-2186, July 1994, and by David Fulkerson, in “SEU Hard Majority Voter for Triple Redundancy”, U.S. Pat. No. 6,667,520, Dec. 23, 2003, (ii) a dual interleave cell (DICE) architecture described by T. Calin, M. Nicolaidis, and R. Velazco, in “Upset hardened memory design for submicron CMOS technology,” IEEE Trans. Nucl. Sci., vol. 43, pp. 2345-2352, December 1996, and by Jerry Dooley, in “SEU-Immune Latch for Gate Array, Standard Cell, and other ASIC Applications,” U.S. Pat. No. 5,311,070, May 10, 1994, (iii) a temporal latch architecture described by D. G. Mavis and P. H. Eaton, in “Temporally Redundant Latch for Preventing Single Event Disruptions in Sequential Integrated Circuits,” U.S. Pat. No. 6,127,864, October 2000., (iv) a current-sharing architecture described by M. P. LaMacchia and W. O. Mathes, in “SEU Hardening Approach for High Speed Logic,” U.S. Pat. No. 5,600,260, and by Paul W. Marshall, Martin A. Carts, Arthur Campbell, Dale McMorrow, Steve Buchner, Ryan Stewart, Barbara Randall, Barry Gilbert, and Robert A. Reed, in “Single Event Effects in Circuit-Hardened SiGe HBT Logic at Gigabit per Second Data Rates,” IEEE Transactions on Nuclear Science, vol. 47, No. 6, December 2000, pp. 2669-2674, and (v) a gated feedback latch architecture described by Ramkumar Krithivasan et al., in “Application of RHBD Techniques to SEU Hardening of Third-Generation SiGe HBT Logic Circuits,” IEEE NSREC, Ponte Vedra Beach, Fla.; Jul. 17-21, 2006.

Only the last two architectures are really suitable for very high-speed applications based on HBTs. It has been shown by G. Niu, R. Krithivasan, J. Cressler et al. cited above that a current-sharing architecture cannot provide the required Anti-SEE protection (ASP) in CML latches. CML latches are the most commonly used cells in digital designs. Thus, a current-sharing architecture cannot be considered a universal approach to the protection of CML cells.

In some respects, the gated feedback latch architecture shown in FIG. 3 is arguably the closest approach to the techniques proposed herein. The latch comprises two pass cells 10 and 20, two storage cells 30 and 40, and two OR gates 50 and 60 implemented as emitter followers. The two pass cells 10 and 20 have two differential data inputs 11/12 and 21/22, respectively. The two storage cells 30 and 40 are provided with feedback through the OR gates 50 and 60.

The gated feedback latch architecture of FIG. 3 provides anti-SEE protection for the HBTs of the pass cells 10 and 20 in case of completely independent data inputs. However, the gated feedback latch architecture of FIG. 3 has several drawbacks. For example, a SEE in any of the storage cell HBTs results in unrecoverable distortion of the corresponding data output voltages 91/92 due to the base current pulse described above. Also, a SEE in any of the HBTs of the OR-gates 50 and 60 results in an erroneous change of state in the storage cells 30 and 40 when operating in the storage mode. Further, a SEE in any of the tail current sources 70 and 80 results in significant distortion of the output signals, as well as a disturbance of the reference voltage 90, which propagates to all cells connected to the same reference node. Additionally, the gated feedback latch architecture of FIG. 3 is actually an emitter-coupled logic (ECL) architecture that utilizes emitter followers for driving both top-level and bottom-level inputs. As a result, ECL gates require higher supply voltages and consume significantly higher power compared to similar CML gates.

SUMMARY OF THE INVENTION

The present invention provides a new approach to the anti-SEE protection of a complete library of basic CML cells without significant degradation of the speed-power performance of those cells.

In accordance with a first aspect of the present invention, method of providing anti-SEE protection of high speed data paths in a cell of a CML integrated circuit comprises the following: converting a SEE induced HBT collector current pulse of the cell to a low voltage level by use of a collector loading resistor; hard limiting collector and base voltages of an HBT of the cell to a level that is lower than a voltage in any undisturbed operational mode of the cell and that is still sufficiently high to prevent any unrecoverable changes of internal node voltages of the cell due to a SEE; providing a low-impedance path for a SEE-induced base current pulse of the cell; and, combining outputs of the cell by use of a logical function utilizing a pair of HBTs having at least base and emitter nodes such that any erroneous voltage at one of the base nodes does not disturb a voltage on the emitter nodes as long as a voltage on the emitter node is lower than the lowest operational level the other of the base nodes, wherein the logical function comprises one of an OR function and a NOR function.

In accordance with a second aspect of the present invention, an integrated circuit having protection of a low-speed path against a SEE comprises a strike sensitive node in the integrated circuit, a node to be protected in the integrated circuit such that the node to be protected is in the low-speed path, and a low-pass filter between the strike sensitive node and the node to be protected. The low-pass filter has a time constant that is a high time constant.

In accordance with a third aspect of the present invention, a voltage shifting unit implementing protection against a SEE, the voltage shifting unit comprises an input, an output, an HBT, a series resistor, and a Schottky diode. The HBT has an emitter node connected to the output and a base node connected to the input. The series resistor is connected between a positive supply rail and a collector node of the HBT, and the resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse. The Schottky diode has an anode connected to the base node of the HBT and a cathode connected to the collector node of the HBT, and the Schottky diode is arranged to provide a low-impedance path for a SEE-induced base current pulse.

In accordance with a fourth aspect of the present invention, a CML tail current source in the form of a current mirror having anti-SEE protection comprises an anti-SEE protected current-defining section, at least one anti-SEE protected current-reproducing section, and a capacitor. The anti-SEE protected current-defining section has an input driven by a current source and having an output connected to a common reference node. The at least one anti-SEE protected current-reproducing section has an input connected to the common reference node and an output that is arranged to supply a mirrored tail current to an associated CML cell. The capacitor forms a low-pass filter with at least one of the current-defining section and the current-reproducing section, the capacitor is coupled to the common reference node, and the low-pass filter has a time constant arranged to provide protection against a SEE.

In accordance with a fifth aspect of the present invention, an EF cell protected against a SEE comprises first and second inputs, an output, first, second, and third HBTs, first and second resistors, first and second Schottky diodes, a degeneration resistor, a voltage limiter, a limiting resistor, and a filtering resistor. The first HBT has a first emitter node connected to the output and a first base node connected to the first input. The first resistor is connected between a positive supply rail and a first collector node of the first HBT, and the first resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse. The first Schottky diode has a first anode connected to the first base node and a cathode connected to the first collector node, and the first Schottky diode is arranged to provide a low-impedance path for a SEE-induced base current pulse. The second HBT has a second emitter node connected to the output and a second base node connected to the second input. The second resistor is connected between the positive supply rail and a second collector node of the second HBT, and the second resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse. The second Schottky diode has a second anode connected to the second base node and a cathode connected to the second collector node, and the second Schottky diode is arranged to provide a low-impedance path for a SEE-induced base current pulse. The third HBT has a third collector node, a third base node, and a third emitter node. The degeneration resistor couples the third emitter node to a negative supply rail. The voltage limiter is connected to the third collector node in order to provide a low-impedance path for a SEE-induced current pulse, and the voltage limiter has an output impedance. The limiting resistor has a value that is much higher than the output impedance of the voltage limiter, and the limiting resistor couples the third collector node to first and second emitters. The filtering resistor couples the base node to a capacitor, and the filtering resistor forms the low-pass filter with the capacitor.

In accordance with a sixth aspect of the present invention, a dual-redundant CML buffer stage having protection against a SEE comprises first and second differential CML inputs arranged to receive logically equivalent but electrically isolated input signals, first and second differential CML outputs arranged to receive logically equivalent but electrically isolated output signals, and an internal processing circuit coupled between the first and second differential CML inputs and the first and second differential CML outputs. The internal processing circuit is arranged to provide protection against a SEE so as to ensure that the output signals are unaffected by particles striking the dual-redundant CML buffer stage.

In accordance with a seventh aspect of the present invention, a dual CML current switch cell having protection against a SEE comprises first and second differential cell inputs, a differential cell output, first and second differential current switches, an anti-SEE protected current-defining section, at least one anti-SEE protected current-reproducing section, a capacitor, first and second resistors, and first voltage and second voltage limiters. The first differential current switch has a first differential switch input, a first switch output, and a first switch source node, wherein the first differential switch input is coupled to the first differential cell input. The second differential current switch has a second differential switch input, a second switch output, and a second switch source node. The second first differential switch input is coupled to the second differential cell input, and the first and second switch outputs are coupled to the differential cell output. The anti-SEE protected current-defining section has an input driven by a current source and has an output connected to a common reference node. The at least one anti-SEE protected current-reproducing section has an input connected to the common reference node and an output coupled to the first and second switch source nodes. The capacitor forms a low-pass filter with at least one of the current-defining section and the current-reproducing section, the capacitor is coupled to the common reference node, and the low-pass filter has a time constant arranged to provide protection against a SEE. The first resistor couples the first switch output to a positive supply rail, and the first resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse. The second resistor couples the second switch output to the positive supply rail, and the second resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse. The first voltage limiter is connected to the first switch output. The second voltage limiter is connected to the second switch output.

In accordance with an eighth aspect of the present invention, a CML logic AND cell comprises first and second top-level differential inputs, a differential output, a standard CML AND gate, first and second voltage limiters, first and second resistors, and a differential current switch. The standard CML AND gate has first and second standard CML AND gate inputs connected to the first top-level differential input and first and second standard CML AND gate outputs connected to the differential output of the cell. The first voltage limiter is coupled to the first standard CML AND gate output. The second voltage limiter is coupled to the second standard CML AND gate output. The first resistor couples the first standard CML AND gate output to a positive supply rail, and the first resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse. The second resistor couples the second standard CML AND gate output to the positive supply rail, and the second resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse. The differential current switch has first and second inputs connected to the second top-level differential input, first and second output nodes connected to the first and second standard CML AND gate outputs, and source nodes coupled to source nodes of the standard CML AND gate.

In accordance with a ninth aspect of the present invention, a CML multiplexer cell comprises first, second, and third top-level differential cell inputs, a bottom-level differential cell input, a differential cell output, first, second, third, fourth, fifth, sixth, seventh, and eighth HBTs, first and second resistors, first and second voltage limiters, a tail current source, and first, second, third, and fourth Schottky diodes. The first and second HBTs have respective first and second emitter nodes, first and second collector nodes, and first and second base nodes. The first and second base nodes are coupled to the first top-level differential cell input. The first resistor couples the first collector node to a positive supply rail, and the first resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse. The second resistor couples the second collector node to the positive supply rail, and the first resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse. The first voltage limiter is coupled to the first collector node, and the second voltage limiter is coupled to the second collector node. The third and fourth HBTs have respective third and fourth emitter nodes, third and fourth collector nodes, and third and fourth base nodes. The third and fourth base nodes are coupled to the second top-level differential cell input, the third collector node is coupled to the first collector node, and the fourth collector node is coupled to the second collector node. The fifth and sixth HBTs have respective fifth and sixth emitter nodes, fifth and sixth collector nodes, and fifth and sixth base nodes. The fifth and sixth base nodes are coupled to the third top-level differential cell input, the fifth collector node is coupled to the first collector node, and the sixth collector node is coupled to the second collector node. The seventh and eighth HBTs have respective seventh and eighth emitter nodes, seventh and eighth collector nodes, and seventh and eighth base nodes. The seventh and eighth base nodes are coupled to the bottom-level differential cell input. The tail current source has an output connected to the seventh and eighth emitters. The first Schottky diode has a first cathode connected to seventh collector node and a first anode connected to the first and second emitter nodes. The second Schottky diode has a second cathode connected to the eighth collector node and a second anode connected to the third and fourth emitter nodes. The third Schottky diode has a third cathode connected to seventh collector node and a third anode connected to the fifth and sixth emitter nodes. The fourth Schottky diode has a fourth cathode connected to the eighth collector node and a fourth anode connected to the fifth and sixth emitter nodes.

In accordance with a tenth aspect of the present invention, a dual-redundant CML logic stage with full protection from SEEs comprises first and second differential stage inputs, first and second differential stage outputs, and first, second, third, and fourth dual current-switching cells. Each of the first, second, third, and fourth dual current-switching cells has first and second cell inputs and a cell output. The first, second, third, and fourth dual current-switching cells are connected in a circle so that the second cell input of the first dual current-switching cell is coupled to the first differential stage input, the first cell input of the second dual current-switching cell is coupled to the cell output of the first dual current-switching cell, the second cell input of the second cell is coupled to the first differential stage input, the cell output of the second dual current-switching cell is coupled to the first differential stage output, the first cell input of the third dual current-switching cell is coupled to the cell output of the second dual current-switching cell, and the second cell input of the third dual current-switching cell is coupled to the second differential stage input, the first cell input of the fourth dual current-switching cell is coupled to the cell output of the third dual current-switching cell, the second cell input of the fourth dual current-switching cell is coupled to the second differential stage input, the cell output of the fourth dual current-switching cell is coupled to the second differential stage output, and the first cell input of the first dual current-switching cell is coupled to the cell output of the fourth dual current-switching cell. Each of the first, second, third, and fourth dual current-switching cells is SEE protected.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which illustrate embodiments of the present invention, include:

FIG. 1 illustrates a model of an HBT under a particle strike as a subcircuit including the basic HBT model and three current pulse sources;

FIG. 2 illustrates the simulated shapes of the current pulses induced by the strike;

FIG. 3 illustrates a schematic of a latch that is SEE-hardened in accordance with a previous technique;

FIG. 4 illustrates a schematic of an ASP dual emitter follower in accordance with one aspect of the present invention;

FIG. 5 illustrates a block diagram of a ASP CML buffer with bottom-level inputs and outputs in accordance with another aspect of the present invention;

FIG. 6 illustrates a block diagram of a ASP CML buffer with top-level inputs and outputs in accordance with still another aspect of the present invention;

FIG. 7 illustrates a schematic of a standard CML buffer for the purpose of illustration;

FIG. 8 illustrates a schematic of a SEE Disturbance Rejection (SDR) dual current switch in accordance with yet another aspect of the present invention;

FIG. 9 illustrates a block diagram of an ASP CML logic stage in accordance with a further aspect of the present invention;

FIG. 10 illustrates a schematic of an ASP n-p-n current mirror in accordance with still a further aspect of the present invention;

FIG. 11 illustrates a schematic of a SDR AND cell in accordance with yet a further aspect of the present invention; and,

FIG. 12 illustrates a schematic of a SDR 2-to-1 multiplexer cell in accordance with an additional aspect of the present invention.

DETAILED DESCRIPTION ASP Techniques for Bottom-Level CML Signals

Anti-SEE protection utilizing logic functions requires a number of sophisticated techniques. Based on the model of a SEE in an HBT presented in FIG. 1, a possible anti-SEE protection approach is the implementation of the logic OR function in the form of common-emitter structures 50/60 shown in FIG. 3. However, the main problem with the OR function implementation based on HBTs is the SEE-initiated negative base current pulse i_(Bp) that increases the base node voltage in all practical cases of the base node termination. This pulse results in an associated increase of the transistor's emitter current and the emitter node voltage, which cannot be rejected by the OR function. Consequently, the gated feedback latch of FIG. 3 does not provide any protection against the SEE in the HBTs of the storage cells 30/40 and in the OR-gates 50/60.

In accordance with an embodiment of the present invention, this problem is solved by an improved common-emitter structure of an anti-SEE protection emitter follower (ASP EF) cell 100 that is shown in FIG. 4. The circuit of the ASP EF cell 100 includes two equivalent voltage-shifting sections 110 a and 110 b with separate inputs 111 a and 111 b and with coupled outputs 112 a and 112 b connected to a common current sink 120 having a tail current I₀. The ASP EF cell 100 operates with two logically equal but electrically isolated signals applied to the inputs 111 a and 111 b of the voltage-shifting sections 110 a and 110 b.

The current sink 120 may be provided in accordance with the current-reconstructing section 820 described below.

The sections 110 a and 110 b includes respective HBTs 113 a and 113 b whose emitter nodes are connected to the corresponding outputs 112 a and 112 b, thus creating a common-emitter node between the two sections 110 a and 110 b. Schottky diodes 115 a and 115 b are connected in parallel with the respective base-collector junctions of corresponding HBTs 113 a and 113 b. The collector nodes of the HBTs 113 a and 113 b are connected to a positive supply rail 1 through corresponding resistors 114 a and 114 b. The resistances R of the resistors 114 a and 114 b are selected in accordance with two restrictions. First, the normal voltage drop RI₀ across the resistors 114 a and 114 b must be low enough to keep the transistors 113 a and 113 b in their active operational region. Second, the SEE-induced voltage drop R(I₀+i_(Cn)) across the resistors 114 a and 114 b must be high enough to open the Schottky diodes 115 a and 115 b in order to establish a low-impedance path for the SEE-generated base currents and to prevent any rise of the base node voltages.

In this case, the SEE-affected voltage-shifting section 110 a or 110 b is turned off so that current through the corresponding HBT is cut off while the output voltage at the common-emitter node is supported by the other voltage-shifting section 110 a or 110 b.

A negligible variation of the output voltage is caused by the change of the current running through the active one of the HBTs 113 a and 113 b.

A similar performance could be achieved without the diodes 115 a and 115 b by utilization of an open base-to-collector junction of the transistors 113 a and 113 b. Unfortunately, this open base-to-collector junction configuration leads to switching of the transistors 113 a and 113 b into the reverse operational mode, which results in reversed emitter current and erroneous low common-emitter node voltage. The Schottky diodes 115 a and 115 b, which open at a significantly lower direct voltage, provide an alternative path for the base currents while keeping the appropriate one of the transistors 113 a and 113 b switched off.

The unconditional protection of the common-emitter node in the described structure of FIG. 4 facilitates two versions of ASP buffers 600 and 700 as shown in FIG. 5 and FIG. 6.

As shown in FIG. 5, the first buffer stage 600 operates with bottom-level CML input/output signals provided by external ASP EF cells and includes two standard CML buffer cells 201 and 202 each being constructed in accordance a buffer cell 200 shown in FIG. 7. The CML buffer cells 201 and 202 accept corresponding input bottom-level differential signals 611/612 and 621/622 and convert these signals into corresponding top-level CML signals 613/614 and 623/624. The direct parts of these signals are applied to the inputs of two ASP EF cells 101 and 103, and the inverted parts of these signals are applied to the inputs of two ASP EF cells 102 and 104.

Each of the ASP EF cells 101, 102, 103, and 104 performs the logic OR function. The ASP EF cells 101 and 102 deliver the first pair of direct and inverted signals 615 and 616 to the first bottom-level differential output of the stage 600. The ASP EF cells 103 and 104 likewise deliver the second pair of direct and inverted signals 625 and 626 to the second bottom-level differential output of the stage 600.) As a result, the first and second differential output signals of the stage 600 are logically equivalent but are electrically isolated.

An instance of the ASP EF cell 100 of FIG. 4 is used for each of the ASP EF cells 101, 102, 103, and 104.

A SEE in any of the switching HBTs 203 and 204 (FIG. 7) of the CML buffer cells 201/202 results in corruption of both input and output signals of the buffers. To avoid big unrecoverable deviations of the voltages on nodes 613, 614, 615, and 616 caused by SEE-induced collector currents, minimum levels of these voltages are limited by limiters 300 a, 300 b, 300 c, and 300 d, each including an HBT diode with its emitter node connected to the output of the corresponding limiter and its joint base and collector nodes connected to a global temperature-stabilized and process-compensated reference voltage 5. The limiters 300 b, 300 c, and 300 d may each be constructed as a transistor coupled so as to form a diode as shown by the limited 300 a in FIG. 4.

This reference voltage can be generated using well-known techniques.

In accordance with the performance of the ASP EF cell described above, it can be seen that both output signals of the stage always stay correct, following the input signal, in spite of SEE-related corruptions of internal signals.

The second buffer stage 700 created in accordance with an embodiment of the present invention has the same internal blocks 101, 102, 103, 104, 201, and 202. But these blocks are placed in a reversed order, with top-level input signals 711, 712, 721, and 722 initially processed by the ASP EF cells 101, 102, 103, and 104 and then shifted up to top-level outputs 715, 716, 725, and 726 by the CML buffer cells 201 and 202. It must be noted that, unlike in the first buffer stage 600, one of the outputs of the second buffer stage 700 is corrupted in the event of a SEE while the other output stays correct.

ASP Techniques for Top-Level CML Signals

Though the ASP EF cells developed in accordance with embodiments of the present invention can provide a complete anti-SEE protection of bottom-level CML signals, the same protection of top-level signals requires different techniques. The logic NOR function performed by a dual current switch 400 as shown in FIG. 8 is capable of rejecting the low erroneous voltages at any one pair of its input differential nodes 411/412 or 413/414, but provides no protection against a SEE in HBTs 415, 416, 417, or 418 of the switch itself. The differential nodes 411/412 and 413/414, for example, may be top-level input nodes.

In this last case, a SEE-induced collector current in the affected transistor (e.g., the HBT 415 or the HBT 416) increases the voltage drop across a corresponding loading resistor 419 or 420, which leads to disturbances of the output voltage at a corresponding collector node 421 or 422 and both input base node voltages 411 and 413 or 412 and 414 associated with the HBTs connected to the corrupted collector node 415/417 or 416/418. Limiting the collector voltages by use of low-impedance voltage limiters 301 a and 301 b can reduce the value of the disturbances, but this voltage limiting of the collector voltages is not enough for the complete protection of the cell.

A current source 423 is coupled to the emitter nodes of HBTs 415, 416, 417, and 418 as shown in FIG. 8 and may be provided in accordance with the current-reconstructing section 820 described below.

In accordance with embodiments of the present invention, this difficulty is rectified by the dual-input/output redundant architecture of an ASP CML logic stage 500 illustrated in FIG. 9. The logic stage 500 includes four equivalent dual CML current switches 401, 402, 403, and 404 with two or more top-level differential inputs, one or more bottom-level differential inputs, and one top-level-level differential output. An instance of the dual current switch 400 may be use for each of the dual CML current switches 401, 402, 403, and 404. Each of the dual CML current switches 401, 402, 403, and 404 shown in FIG. 9 has three top-level differential inputs and one bottom-level input. However, for the purpose of generalization, cells with two or more top-level inputs and one or more bottom-level input may be used in FIG. 9. Thus, in the case where the dual current switch 400 is used for each of the dual CML current switches 401, 402, 403, and 404, the dual CML current switches 401, 402, 403, and 404 would have only two top-level differential inputs and one bottom-level input.

The current switches 401, 402, 403, and 404 are connected in a circle in such a way that the differential output of a previous cell is connected to the first top-level differential input of the next cell. The second top-level differential inputs of cells 401 and 402 are both connected to top-level differential input 511/512 of the logic stage 500, while the second top-level differential inputs of cells 403 and 404 are both connected to top-level differential input 521/522 of the logic stage 500. The third top-level differential inputs of cells 401 and 402 are both connected to top-level differential input 513/514 of logic stage 500, while the second top-level differential inputs of cells 403 and 404 are both connected to top-level differential input 523/524 of logic stage 500. The bottom-level differential inputs of cells 401 and 402 are both connected to bottom-level differential input 515/516 of logic stage 5001 while the bottom-level differential inputs of cells 403 and 404 are both connected to bottom-level differential input 525/526 of logic stage 500. The output of cells 402 and 404 are correspondingly connected to top-level differential outputs 517/518 and 527/528 of the logic stage 500.

As can be seen from FIG. 9, a SEE in any individual cell (e.g., the current switch 402) corrupts three signals associated with the inputs/outputs of this cell, which may include one input and one output of the logic stage 500 (in this case, 511/512 or 513/514 and 517/518). However, the other input and output of the logic stage 500 (in this case, 521/522, 523/524, and 527/528) are undisturbed.

A limiting unit is coupled to the output nodes of the dual CML current switch 401, a limiting unit is coupled to the output nodes of the dual CML current switch 402, a limiting unit is coupled to the output nodes of the dual CML current switch 403, and a limiting unit is coupled to the output nodes of the dual CML current switch 404. These limiting units are not shown in FIG. 9 but are derived from the dual current switch 400 shown in FIG. 8.

ASP Techniques for Tail Current Sources and Current Mirrors

The tail current sources of CML cells are created as current-reproducing sections of a multi-output n-p-n current mirror. In accordance with the present invention, an ASP n-p-n current mirror 800 is shown in FIG. 10 and includes a current-defining section 810 that is driven by a certain current source 830 and supplies a certain reference voltage to one or more current-reconstructing (mirror) sections 820 through a local reference line 3. The local reference line 3 is always decoupled from a negative supply rail 2 by a large capacitor 4.

In accordance with embodiments of the present invention, each section 820 includes a HBT 821 whose emitter node is connected to the negative supply rail 2 through a degeneration resistor 822 and whose base node is connected to the local reference line 3 through a filtering resistor 823. A collector node of the HBT 821 is directly connected to a low-impedance output of a voltage limiter 302 and is connected to a current-sinking output 824 through a limiting resistor 825.

A SEE-induced current pulse through the collector node of the HBT 821 flows partly through the resistor 825, thus causing a drop of the collector node voltage that opens the voltage limiter 302. As a result, the main part of the SEE-induced current flows through the voltage limiter 302 and thus causes minimum disturbance of the cell's tail current. The efficiency of this protection depends on the ratio between the values of the resistance of the resistor 825 and the output resistance of the voltage limiter 302, and is restricted by the tolerable voltage drop across the resistor 825 in the normal operational mode. Accordingly, the resistance of the resistor 825 should have a value that is much higher than the value of the output resistance of the voltage limiter 302. The SEE-induced base current pulses are suppressed in the same way by means of the resistor 823 and the base-collector junction of the HBT 821. A low-pass filter comprising the resistor 823 and the capacitor 4 effectively filters out the resulting base node voltage pulses, thus keeping the local reference line 3 undisturbed.

In accordance with embodiments of the present invention, the current-defining section 810 includes a HBT 811 whose emitter node is connected to the negative supply rail 2 through a degeneration resistor 812 and whose base node is connected to the local reference line 3 through a filtering resistor 813. The current into the local reference line 3 is provided through the output 112 of the voltage-shifting unit 110 shown in FIG. 4. The input 111 of the voltage-shifting unit 110 is connected to the collector node of the HBT 811, thus creating a diode-like structure. The parameters of these components are related to those of similar components in the section 820 in accordance with the well-known theory of the current mirror operation.

SEE-related disturbances of the voltage on the local reference line 3 can be associated with either the HBT 811, or with the voltage-shifting unit 110. SEE-induced current pulses in the HBT 811 manifest themselves as negative voltage pulses at the collector node of the transistor. The resulting low collector voltage closes the HBT of the voltage-shifting unit 110 and is then filtered out by a low-pass filter comprising the reverse-biased base-emitter junction of the transistor 113 a or 113 b and the decoupling capacitor 4. Base current pulses are suppressed in the same way as in the voltage-shifting unit 810.

Examples of 2-Level SDR CML Cells

The schematics of two main 2-level CML cells 210 and 230, utilizing the ASP techniques described herein, are shown respectively in FIG. 11 and FIG. 12. To achieve anti-SEE protection, the cells 210 and 230 should be incorporated into the architecture shown in FIG. 9.

The first cell 210 shown in FIG. 11 performs the logic AND function and comprises a standard CML AND gate with two switching HBTs 223 and 224, a top-level differential input 211/212 coupled to the bases of the two switching HBTs 223 and 224, a bottom-level differential input 213/214 coupled to the bases of two HBTs 226 and 227, an ASP tail current source 215, and the voltage limiters 303 a and 303 b coupled to the collectors of the two switching HBTs 223 and 224 and to outputs 217/218 of the first cell 210. The emitters of the HBTs 226 and 227 are connected to the ASP tail current source 215, the bases of the HBTs 226 and 227 are connected to bottom-level differential input 213/214, and the collector of the HBT 226 is connected to the emitters of the HBTs 223 and 224 and to the emitters of two additional HBTs 219 and 220. The two additional HBTs 219 and 220 are connected to an additional top-level differential input 221/222. The emitter of an HBT 228 is connected to the collector the HBT 227, the collector of the HBT 228 is connected to the output 217, and the base of the HBT 228 is connected to the positive voltage rail 1. The HBTs 219 and 220 create a dual current switch with the top-level switching transistors 223 and 224 in order to implement the SDR technique in accordance with an aspect of the present invention.

The current-reconstructing section 820 of the current mirror 800 discussed below may be used for the ASP tail current source 215.

The second cell 230 shown in FIG. 12 represents a 2-to-1 CML multiplexer and includes a standard CML multiplexer gate with top-level differential inputs 231/232 and 233/234, bottom-level differential input 235/236, an ASP tail current source 237, and voltage limiters 304 a and 304 b for outputs 239/240 of the cell 230.

The current-reconstructing section 820 of the current mirror 800 discussed below may be used for the ASP tail current source 237.

The implementation of the SDR technique in the cell 230 would require two additional pairs of HBTs to create dual current switches with the top-level differential pairs of HBTs 241/242 and 243/244. To minimize the additional capacitance introduced by additional transistors to the input and output nodes of the cell 230, the cell 230 incorporates a single additional pair of HBTs 245/246 connected to an additional top-level differential input 247/248. The HBTs 245/246 can create a dual current switch both with the HBTs 241/242 and with the HBTs 243/244, depending on the states of the bottom-level switching transistors 245/246.

The selection is performed by means of logic OR functions implemented as two pairs of Schottky diodes 249/250 and 251/252, which are inserted between the bottom and top levels of the cell 230 as shown in FIG. 12.

The bases of HBTs 253 and 254 are connected respectively to bottom-level differential inputs 235 and 236. The emitters of the HBTs 253 and 254 are connected to the ASP tail current source 237, the collector of the HBT 253 is connected to the cathodes of the Schottky diodes 249 and 250, and the collector of the HBT 254 is connected to the cathodes of the Schottky diodes 251 and 252. The anode of the Schottky diode 249 is connected to the emitters of the HBTs 241 and 242, the anode of the Schottky diode 252 is connected to the emitters of the HBTs 243 and 244, and the anodes of the Schottky diodes 250 and 251 are both connected together and to both of the emitters of the HBTs 245 and 246.

The ASP n-p-n current mirror 800 may be used for the ASP tail current source 237. In this case, the output 824 of the ASP n-p-n current mirror 800 is connected to the common emitter nodes of the bottom-level HBTs 247 and 248.

The collector nodes of the HBTs 241, 243, and 245 are connected to the output node 240 of the cell 230, to the output node of the voltage limiter 304 a, and to the positive rail 1 through a loading resistor 255. The collector nodes of the HBTs 242, 244, and 246 are connected to the output node 239 of the cell 230, to the output node of the voltage limiter 304 b, and to the positive rail 1 through a loading resistor 256.

In accordance with the well-known specifics of the CML architecture, the cell 230 can be converted into other main CML cells, such as a latch cell and an XOR cell, by cross-connection of the input 233/234 either to the output 239/240, or to the input 231/232. As can be understood, this does not affect the anti-SEE protection achieved in accordance with the present invention.

There are many aspects of the present invention as described above. Modifications of the present invention will occur to those practicing in the art of the present invention. Accordingly, the description of the present invention is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and the exclusive use of all modifications which are within the scope of the appended claims is reserved. 

1. A method of providing anti-SEE protection of high speed data paths in a cell of a CML integrated circuit comprising: converting a SEE induced HBT collector current pulse of the cell to a low voltage level by use of a collector loading resistor; hard limiting collector and base voltages of an HBT of the cell to a level that is lower than a voltage in any undisturbed operational mode of the cell and that is still sufficiently high to prevent any unrecoverable changes of internal node voltages of the cell due to a SEE; providing a low-impedance path for a SEE-induced base current pulse of the cell; and, combining outputs of the cell by use of a logical function utilizing a pair of HBTs having at least base and emitter nodes such that any erroneous voltage at one of the base nodes does not disturb a voltage on the emitter nodes as long as a voltage on the emitter node is lower than the lowest operational level the other of the base nodes, wherein the logical function comprises one of an OR function and a NOR function.
 2. The method of claim 1 wherein the combining of outputs comprises OR'ing the outputs utilizing the pair of HBTs with common emitter nodes and separate base and collector nodes such that any erroneous voltage at one of the base nodes does not disturb a voltage on the emitter nodes as long as a level of the voltage on the common emitter node is lower than the lowest operational level on the other of the base nodes.
 3. The method of claims 1 wherein the combining of outputs comprises NOR'ing the outputs utilizing the pair of HBTs with common emitter nodes, separate base nodes, and common collector nodes such that any erroneous voltage at one of the base nodes does not disturb a voltage on the emitter nodes as long as a level of the voltage on the common collector node is lower than the lowest operational level on the other of the base nodes.
 4. An integrated circuit having protection of a low-speed path against a SEE comprising: a strike sensitive node in the integrated circuit; a node to be protected in the integrated circuit, wherein the node to be protected is in the low-speed path; and, a low-pass filter between the strike sensitive node and the node to be protected, wherein the low-pass filter has a time constant that is a high time constant.
 5. The integrated circuit of claim 4 wherein the low-pass filter comprises a resistor and a capacitor, wherein the resistor is between the strike-sensitive node and the node to be protected, wherein the capacitor is coupled to the node to be protected, and wherein the time constant is defined by the resistor and the capacitor.
 6. A voltage shifting unit implementing protection against a SEE, the voltage shifting unit comprising: an input; an output; an HBT having an emitter node connected to the output and a base node connected to the input; a series resistor connected between a positive supply rail and a collector node of the HBT, wherein the resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse; and, a Schottky diode having an anode connected to the base node of the HBT and a cathode connected to the collector node of the HBT, wherein the Schottky diode is arranged to provide a low-impedance path for a SEE-induced base current pulse.
 7. The voltage shifting unit of claim 6 wherein: the resistor comprises a first resistor; the Schottky diode comprises a first Schottky diode; the HBT comprises a first HBT; the voltage shifting unit further comprises a second resistor, a second Schottky diode, and a second HBT having an emitter node coupled to the emitter node of the first HBT; the first resistor is coupled between the positive supply rail and the collector node of the first HBT and the second resistor is coupled between the positive supply rail and a collector node of the second HBT; the first and second resistors are arranged to convert SEE-induced current pulses into negative voltage pulses; and, the second Schottky diode has an anode connected to a base node of the second HBT and a cathode connected to the collector node of the second HBT.
 8. The voltage shifting unit of claim 7 wherein the input comprises a first input, wherein the output comprises a first output, wherein the first HBT, the first resistor, and the first Schottky diode form a first voltage-shifting unit having the first input and the first output, wherein the second HBT, the second resistor, and the second Schottky diode form a second voltage-shifting unit having a second input and a second output, wherein the first and second inputs are connected to receive two logically equivalent but electrically isolated input signals, and wherein the first and second outputs are jointly connected as an output of the voltage shifting unit and to a current-sink.
 9. A CML tail current source in the form of a current mirror having anti-SEE protection comprising: an anti-SEE protected current-defining section having an input driven by a current source and having an output connected to a common reference node; at least one anti-SEE protected current-reproducing section having an input connected to the common reference node and an output that is arranged to supply a mirrored tail current to an associated CML cell; and, a capacitor forming a low-pass filter with at least one of the current-defining section and the current-reproducing section, wherein the capacitor is coupled to the common reference node, and wherein the low-pass filter has a time constant arranged to provide protection against a SEE.
 10. The CML tail current source of claim 9 wherein the current-defining section comprises: an HBT having a collector node, a base node, and an emitter node, wherein the collector node is connected to an input of the CML tail current source; a degeneration resistor coupling the emitter node to a negative supply rail; and, a filtering resistor coupling the base node to the capacitor so as to form the low-pass filter.
 11. The CML tail current source of claim 10 wherein the current-reproducing section comprises: an HBT having a collector node, a base node, and an emitter node; a degeneration resistor coupling the emitter node to a negative supply rail; a voltage limiter connected to the collector node in order to provide a low-impedance path for a SEE-induced current pulse, wherein the voltage limiter has an output impedance; a limiting resistor having a value that is much higher than the output impedance of the voltage limiter, wherein the limiting resistor couples the collector node to an output of the CML tail current source; and, a filtering resistor coupling the base node to the capacitor, wherein the filtering resistor forms the low-pass filter with the capacitor.
 12. An EF cell protected against a SEE comprising: first and second inputs; an output; a first HBT having a first emitter node connected to the output and a first base node connected to the first input; a first resistor connected between a positive supply rail and a first collector node of the first HBT, wherein the first resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse; a first Schottky diode having a first anode connected to the first base node and a cathode connected to the first collector node, wherein the first Schottky diode is arranged to provide a low-impedance path for a SEE-induced base current pulse; a second HBT having a second emitter node connected to the output and a second base node connected to the second input; a second resistor connected between the positive supply rail and a second collector node of the second HBT, wherein the second resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse; a second Schottky diode having a second anode connected to the second base node and a cathode connected to the second collector node, wherein the second Schottky diode is arranged to provide a low-impedance path for a SEE-induced base current pulse; a third HBT having a third collector node, a third base node, and a third emitter node; a degeneration resistor coupling the third emitter node to a negative supply rail; a voltage limiter connected to the third collector node in order to provide a low-impedance path for a SEE-induced current pulse, wherein the voltage limiter has an output impedance; a limiting resistor having a value that is much higher than the output impedance of the voltage limiter, wherein the limiting resistor couples the third collector node to first and second emitters; and, a filtering resistor coupling the base node to a capacitor, wherein the filtering resistor forms the low-pass filter with the capacitor.
 13. A dual-redundant CML buffer stage having protection against a SEE comprising: first and second differential CML inputs arranged to receive logically equivalent but electrically isolated input signals; first and second differential CML outputs arranged to receive logically equivalent but electrically isolated output signals; and, an internal processing circuit coupled between the first and second differential CML inputs and the first and second differential CML outputs, wherein the internal processing circuit is arranged to provide protection against a SEE so as to ensure that the output signals are unaffected by particles striking the dual-redundant CML buffer stage.
 14. The dual-redundant CML buffer stage of claim 13 wherein the input and output signals comprises corresponding bottom-level input and output CML signals.
 15. The dual-redundant CML buffer stage of claim 13 wherein the input and output signals comprises corresponding top-level input and output CML signals.
 16. The dual-redundant CML buffer stage of claim 13 wherein the first and second differential CML inputs comprise first and second buffer stage bottom-level differential inputs, wherein the first and second differential CML outputs comprise first and second buffer stage bottom-level differential outputs, and wherein the internal processing circuit comprises: a first CML buffer cell having a first direct output, a first inverted output, and a first differential input, wherein the first differential input is connected to the first buffer stage bottom-level differential input; a second CML buffer cell having a second direct output, a second inverted output, and a second differential input, wherein the second differential input is connected to the second buffer stage bottom-level differential input; four equivalent voltage limiters connected respectively to the first and second direct and inverted outputs; and, first, second, third, and fourth emitter followers having corresponding first, second, third, and fourth emitter follower outputs and each having protection against SEES, wherein the four emitter followers couple the outputs of the first and second buffer cells to the buffer stage bottom-level differential outputs in such a way that the first direct output is connected to first inputs of the first and third emitter followers, the second direct output is connected to second inputs of the first and third emitter followers, the first inverted output is connected to first inputs of the second and fourth emitter followers, and the second inverted output is connected to second inputs of the second and fourth emitter followers, wherein the first and second emitter follower outputs provide the first buffer stage bottom-level differential output, and wherein the third and fourth emitter follower outputs provide the second buffer stage bottom-level differential output.
 17. The dual-redundant CML buffer stage of claim 13 wherein the first differential CML input comprises first and second buffer stage top-level inputs forming a first buffer stage top-level differential input, wherein the second differential CML input comprises third and fourth buffer stage top-level inputs forming a second buffer stage top-level differential input, wherein the first and second differential CML outputs comprise first and second buffer stage top-level differential outputs, and wherein the internal processing circuit comprises: a first CML buffer cell having a first direct input, a first inverted input, a first direct output, and a first inverted output, wherein the first direct output and the first inverted output provide the first buffer stage top-level differential output; a second CML buffer cell having a second direct input, a second inverted input, a second direct output, and a second inverted output, wherein the second direct output and the second inverted output provide the second buffer stage top-level differential output; four equivalent voltage limiters connected respectively to the first and second direct and inverted outputs; and, first, second, third, and fourth emitter followers having corresponding first, second, third, and fourth emitter follower outputs and each having protection against SEEs, wherein the first emitter follower output is coupled to the first direct input, wherein the second emitter follower output is coupled to the first inverted input, wherein the third emitter follower output is coupled to the second direct input, wherein the fourth emitter follower output is coupled to the second inverted input, wherein the first buffer stage top-level input is connected to first inputs of the first and third emitter followers, wherein the second buffer stage top-level input is connected to first inputs of the second and fourth emitter followers, wherein the third buffer stage top-level input is connected to second inputs of the first and third emitter followers, and wherein the fourth buffer stage top-level input is connected to second inputs of the second and fourth emitter followers.
 18. A dual CML current switch cell having protection against a SEE comprising: first and second differential cell inputs; a differential cell output; a first differential current switch having a first differential switch input, a first switch output, and a first switch source node, wherein the first differential switch input is coupled to the first differential cell input; a second differential current switch having a second differential switch input, a second switch output, and a second switch source node, wherein the second first differential switch input is coupled to the second differential cell input, and wherein the first and second switch outputs are coupled to the differential cell output; an anti-SEE protected current-defining section having an input driven by a current source and having an output connected to a common reference node; at least one anti-SEE protected current-reproducing section having an input connected to the common reference node and an output coupled to the first and second switch source nodes; a capacitor forming a low-pass filter with at least one of the current-defining section and the current-reproducing section, wherein the capacitor is coupled to the common reference node, and wherein the low-pass filter has a time constant arranged to provide protection against a SEE; a first resistor coupling the first switch output to a positive supply rail, wherein the first resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse; a second resistor coupling the second switch output to the positive supply rail, wherein the second resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse; a first voltage limiter connected to the first switch output; and, a second voltage limiter connected to the second switch output.
 19. The dual CML current switch cell of claim 18 wherein the first differential current switch comprises first and second HBTs having corresponding first and second bases forming the first differential switch input, first and second collectors forming the first switch output, and first and second emitters forming the first switch source node, and wherein the second differential current switch comprises third and second HBTs having corresponding third and fourth bases forming the second differential switch input, third and fourth collectors forming the second switch output, and third and fourth emitters forming the second switch source node.
 20. A CML logic AND cell comprising: first and second top-level differential inputs; a differential output; a standard CML AND gate having first and second standard CML AND gate inputs connected to the first top-level differential input and first and second standard CML AND gate outputs connected to the differential output of the cell; a first voltage limiter coupled to the first standard CML AND gate output; a second voltage limiter coupled to the second standard CML AND gate output; a first resistor coupling the first standard CML AND gate output to a positive supply rail, wherein the first resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse; a second resistor coupling the second standard CML AND gate output to the positive supply rail, wherein the second resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse; and, a differential current switch having first and second inputs connected to the second top-level differential input, first and second output nodes connected to the first and second standard CML AND gate outputs, and source nodes coupled to source nodes of the standard CML AND gate.
 21. The CML logic AND cell of claim 20 further comprising a bottom-level differential input, wherein the standard CML AND gate comprises first and second HBTs having respective common first and second emitter nodes forming the source nodes of the standard CML AND gate, separate first and second base nodes coupled to the first top-level differential input, and separate first and second collector nodes coupled to the differential output, wherein the first resistor couples the collector node of the first HBT to the positive supply rail, wherein the second resistor couples the collector node of the second HBT to the positive supply rail, wherein the first voltage limiter is coupled to the collector node of the first HBT, and wherein the second voltage limiter is coupled to the collector of the second HBT; wherein the differential current switch comprises third and fourth HBTs having respective common third and fourth emitter nodes coupled to the first and second emitter nodes, separate third and fourth base nodes coupled to the second top-level differential input, and separate third and fourth collector nodes, wherein the third and fourth collector nodes are connected respectively to the first and second collector nodes; wherein the CML logic AND cell further comprises fifth, sixth, and seventh HBTs having corresponding fifth, sixth, and seventh base nodes, fifth, sixth, and seventh collector nodes, and fifth, sixth, and seventh emitter nodes, wherein the fifth and sixth base nodes are connected to a bottom-level differential input, wherein the seventh base node is connected to the positive supply rail, wherein the fifth collector node is connected to the first, second, third, and fourth emitter nodes, wherein the sixth collector node is connected to the seventh emitter node, wherein the seventh collector node is connected to one of the first and second collector nodes, and wherein the fifth and sixth emitter nodes are connected to SEE protected current source.
 22. A CML multiplexer cell comprising: first, second, and third top-level differential cell inputs; a bottom-level differential cell input; a differential cell output; first and second HBTs having respective first and second emitter nodes, first and second collector nodes, and first and second base nodes, wherein the first and second base nodes are coupled to the first top-level differential cell input; a first resistor coupling the first collector node to a positive supply rail, wherein the first resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse; a second resistor coupling the second collector node to the positive supply rail, wherein the first resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse; a first voltage limiter coupled to the first collector node; a second voltage limiter coupled to the second collector node; third and fourth HBTs having respective third and fourth emitter nodes, third and fourth collector nodes, and third and fourth base nodes, wherein the third and fourth base nodes are coupled to the second top-level differential cell input, wherein the third collector node is coupled to the first collector node, and wherein the fourth collector node is coupled to the second collector node; fifth and sixth HBTs having respective fifth and sixth emitter nodes, fifth and sixth collector nodes, and fifth and sixth base nodes, wherein the fifth and sixth base nodes are coupled to the third top-level differential cell input, wherein the fifth collector node is coupled to the first collector node, and wherein the sixth collector node is coupled to the second collector node; seventh and eighth HBTs having respective seventh and eighth emitter nodes, seventh and eighth collector nodes, and seventh and eighth base nodes, wherein the seventh and eighth base nodes are coupled to the bottom-level differential cell input; a tail current source having an output connected to the seventh and eighth emitters; a first Schottky diode having a first cathode connected to seventh collector node and a first anode connected to the first and second emitter nodes; a second Schottky diode having a second cathode connected to the eighth collector node and a second anode connected to the third and fourth emitter nodes; a third Schottky diode having a third cathode connected to seventh collector node and a third anode connected to the fifth and sixth emitter nodes; and, a fourth Schottky diode having a fourth cathode connected to the eighth collector node and a fourth anode connected to the fifth and sixth emitter nodes.
 23. The CML multiplexer cell of claim 22 wherein one of the first and second top-level differential inputs is coupled to the differential output so as to form a CML latch.
 24. The CML multiplexer cell of claim 22 wherein one of the first and second top-level differential inputs is inversely coupled to the other of the first and second top-level differential inputs so as to form an XOR cell.
 25. A dual-redundant CML logic stage with full protection from SEEs comprising: first and second differential stage inputs; first and second differential stage outputs; and, first, second, third, and fourth dual current-switching cells each having first and second cell inputs and a cell output, wherein the first, second, third, and fourth dual current-switching cells are connected in a circle so that the second cell input of the first dual current-switching cell is coupled to the first differential stage input, the first cell input of the second dual current-switching cell is coupled to the cell output of the first dual current-switching cell, the second cell input of the second cell is coupled to the first differential stage input, the cell output of the second dual current-switching cell is coupled to the first differential stage output, the first cell input of the third dual current-switching cell is coupled to the cell output of the second dual current-switching cell, and the second cell input of the third dual current-switching cell is coupled to the second differential stage input, the first cell input of the fourth dual current-switching cell is coupled to the cell output of the third dual current-switching cell, the second cell input of the fourth dual current-switching cell is coupled to the second differential stage input, the cell output of the fourth dual current-switching cell is coupled to the second differential stage output, and the first cell input of the first dual current-switching cell is coupled to the cell output of the fourth dual current-switching cell, wherein each of the first, second, third, and fourth dual current-switching cells is SEE protected.
 26. The dual-redundant CML logic stage of claim 25 wherein each of the first, second, third, and fourth dual current-switching cells comprises: a first differential current switch having an input comprising the first cell input of a corresponding dual current-switching cell, having an output comprising the cell output of the corresponding dual current-switching cell, and having a first switch source node; a second differential current switch having an input comprising the second cell input of the corresponding dual current-switching cell, having an output coupled to the cell output of the corresponding dual current-switching cell, and having a second switch source node; an anti-SEE protected current-defining section having an input driven by a current source and having an output connected to a common reference node; at least one anti-SEE protected current-reproducing section having an input connected to the common reference node and an output coupled to the first and second switch source nodes; a capacitor forming a low-pass filter with at least one of the current-defining section and the current-reproducing section, wherein the capacitor is coupled to the common reference node, and wherein the low-pass filter has a time constant arranged to provide protection against a SEE; a resistor coupling the corresponding one of the cell outputs to a positive supply rail, wherein the first resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse; and, a voltage limiter connected to the corresponding one of the cell outputs.
 27. The dual-redundant CML logic stage of claim 25 wherein each of the first, second, third, and fourth dual current-switching cells comprises: a standard CML AND gate having first and second standard CML AND gate inputs respectively comprising the first and second cell inputs of a corresponding dual current-switching cell and having first and second standard CML AND gate outputs comprising the cell output of the corresponding dual current-switching cell; a voltage limiter coupled to the cell output of the corresponding dual current-switching cell; a resistor coupling the cell output of the corresponding dual current-switching cell to a positive supply rail, wherein the resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse; and, an additional differential current switch having an additional input and an output node connected to the cell output of the corresponding dual current-switching cell.
 28. The dual-redundant CML logic stage of claim 25 wherein each of the first, second, third, and fourth dual current-switching cells comprises: first and second HBTs having respective first and second emitter nodes, first and second collector nodes, and first and second base nodes, wherein the first and second base nodes are coupled to the first cell input of a corresponding dual current-switching cell, and wherein the first and second collector nodes are coupled to the cell output of the corresponding dual current-switching cell; a first resistor coupling the first collector node to a positive supply rail, wherein the first resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse; a second resistor coupling the second collector node to the positive supply rail, wherein the first resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse; a first voltage limiter coupled to the first collector node; a second voltage limiter coupled to the second collector node; third and fourth HBTs having respective third and fourth emitter nodes, third and fourth collector nodes, and third and fourth base nodes, wherein the third and fourth base nodes are coupled to the second cell input of the corresponding dual current-switching cells wherein the third collector node is coupled to the first collector node, and wherein the fourth collector node is coupled to the second collector node; fifth and sixth HBTs having respective fifth and sixth emitter nodes, fifth and sixth collector nodes, and fifth and sixth base nodes, wherein the fifth and sixth base nodes are coupled to a third cell input of the corresponding dual current-switching cell, wherein the fifth collector node is coupled to the first collector node, and wherein the sixth collector node is coupled to the second collector node; seventh and eighth HBTs having respective seventh and eighth emitter nodes, seventh and eighth collector nodes, and seventh and eighth base nodes, wherein the seventh and eighth base nodes are coupled to a fourth cell input of the corresponding dual current-switching cell; a tail current source having an output connected to the seventh and eighth emitters; a first Schottky diode having a first cathode connected to seventh collector node and a first anode connected to the first and second emitter nodes; a second Schottky diode having a second cathode connected to the eighth collector node and a second anode connected to the third and fourth emitter nodes; a third Schottky diode having a third cathode connected to seventh collector node and a third anode connected to the fifth and sixth emitter nodes; and, a fourth Schottky diode having a fourth cathode connected to the eighth collector node and a fourth anode connected to the fifth and sixth emitter nodes. wherein one of the first and second cell inputs of the corresponding dual current-switching cell is coupled to the cell output of the corresponding dual current-switching cell so as to form a CML latch.
 29. The dual-redundant CML logic stage of claim 25 wherein each of the first, second, third, and fourth dual current-switching cells comprises: first and second HBTs having respective first and second emitter nodes, first and second collector nodes, and first and second base nodes, wherein the first and second base nodes are coupled to the first cell input of a corresponding dual current-switching cell, and wherein the first and second collector nodes are coupled to the cell output of the corresponding dual current-switching cell; a first resistor coupling the first collector node to a positive supply rail, wherein the first resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse; a second resistor coupling the second collector node to the positive supply rail, wherein the first resistor is arranged to convert a SEE-induced current pulse into a negative voltage pulse; a first voltage limiter coupled to the first collector node; a second voltage limiter coupled to the second collector node; third and fourth HBTs having respective third and fourth emitter nodes, third and fourth collector nodes, and third and fourth base nodes, wherein the third and fourth base nodes are coupled to the second cell input of the corresponding dual current-switching cell, wherein the third collector node is coupled to the first collector node, and wherein the fourth collector node is coupled to the second collector node; fifth and sixth HBTs having respective fifth and sixth emitter nodes, fifth and sixth collector nodes, and fifth and sixth base nodes, wherein the fifth and sixth base nodes are coupled to a third cell input of the corresponding dual current-switching cell, wherein the fifth collector node is coupled to the first collector node, and wherein the sixth collector node is coupled to the second collector node; seventh and eighth HBTs having respective seventh and eighth emitter nodes, seventh and eighth collector nodes, and seventh and eighth base nodes, wherein the seventh and eighth base nodes are coupled to a fourth cell input of the corresponding dual current-switching cell; a tail current source having an output connected to the seventh and eighth emitters; a first Schottky diode having a first cathode connected to seventh collector node and a first anode connected to the first and second emitter nodes; a second Schottky diode having a second cathode connected to the eighth collector node and a second anode connected to the third and fourth emitter nodes; a third Schottky diode having a third cathode connected to seventh collector node and a third anode connected to the fifth and sixth emitter nodes; and, a fourth Schottky diode having a fourth cathode connected to the eighth collector node and a fourth anode connected to the fifth and sixth emitter nodes. wherein one of the first and second cell inputs of the corresponding dual current-switching cell is inversely coupled to the other of the first and second cell inputs of the corresponding dual current-switching cell so as to form an XOR cell 